Quadruple 2-Input Positive-AND Gate (Rev. C)0 pages

74AC11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCAS014C – AUGUST 1987 – REVISED APRIL 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICE (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
This device contains four independent 2-input AND gates. It performs the Boolean function
Y A • B or Y AB in positive logic.
The 74AC11008 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H H H
L X L
X L L
logic symbol†
1
1A
16
1B
1Y
2
15
2A
14
2B
2Y
3
11
3A
10
3B
3Y
6
9
4A
8
4B
4Y
7
&
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date. Copyright W 1996, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
2Y
GND
GND
3Y
4Y
4B
1B
2A
2B
VCC
VCC
3A
3B
4A
D, N, OR PW PACKAGE
(TOP VIEW)