AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted0 pages

12-Bit, 2.0 GSPS, 1.3 V/2.5 V
Analog-to-Digital Converter
AD9625

Data Sheet

FUNCTIONAL BLOCK DIAGRAM
AVDD

AGND

REFERENCE

DRVDD DRGND

DIGITAL INTERFACE
AND CONTROL

VCM
VIN+
VIN–

ADC
CORE

DDC

fS/8 OR fS/16

SERDOUT[0]±
SERDOUT[1]±
SERDOUT[2]±
SERDOUT[3]±
SERDOUT[4]±
SERDOUT[5]±
SERDOUT[6]±
SERDOUT[7]±

RBIAS
CONTROL
REGISTERS

SYSREF±
CLK±

CLOCK
MANAGEMENT

AD9625

CMOS DIGITAL
INPUT/OUTPUT

SDIO

SCLK

CMOS
DIGITAL
INPUT/
OUTPUT

FD

LVDS
DIGITAL
INPUT/
OUTPUT

SYNCINB±

RSTB
IRQ

DIVCLK±

11814-001

12-bit 2.0 GSPS ADC, no missing codes
SFDR = 80 dBc, AIN up to 1 GHz at −1 dBFS, 2.0 GSPS
SFDR = 76 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.0 GSPS
SNR = 59 dBFS, AIN up to 1 GHz at −1 dBFS, 2.0 GSPS
SNR = 58 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.0 GSPS
Noise floor = −149.5 dBFS/Hz at 2.0 GSPS
Power consumption: 3.5 W at 2.0 GSPS
Differential analog input: 1.1 V p-p
Differential clock input
High speed 6- or 8-lane JESD204B serial output
Subclass 1: 5.0 Gbps at 2.0 GSPS
Two independent decimate by 8 or decimate by 16 filters
with 10-bit NCOs
Supply voltages: 1.3 V, 2.5 V
Serial port control
Flexible digital output modes
Built-in selectable digital test patterns

JESD204B
INTERFACE

FEATURES

CSB

Figure 1.

APPLICATIONS
Spectrum analyzers
Military communications
Radar
High performance digital storage oscilloscopes
Active jamming/antijamming
Electronic surveillance and countermeasures

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD9625 is a 12-bit monolithic sampling analog-to-digital
converter (ADC) that operates at conversion rates of up to
2.0 giga samples per second (GSPS). This product is designed
for sampling wide bandwidth analog signals up to the second
Nyquist zone. The combination of wide input bandwidth, high
sampling rate, and excellent linearity of the AD9625 is ideally
suited for spectrum analyzers, data acquisition systems, and a
wide assortment of military electronics applications, such as
radar and jamming/antijamming measures.

1.
2.
3.

High performance: exceptional SFDR in high sample rate
applications, direct RF sampling, and on-chip reference.
Flexible digital data output formats based on the JESD204B
specification.
Control path SPI interface port that supports various
product features and functions, such as data formatting,
gain, and offset calibration values.

The analog input, clock, and SYSREF± signals are differential
inputs. The JESD204B-based high speed serialized output is
configurable in a variety of one-, two-, four-, six-, or eight-lane
configurations. The product is specified over the industrial
temperature range of −40°C to +85°C.

Rev. 0

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