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AD5362/AD5363: 8-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC Data Sheet (Rev. A)0 pages
8-Channel, 16-/14-Bit,
Serial Input, Voltage Output DAC
AD5362/AD5363
FEATURES
8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output voltage spans available
Thermal shutdown function
Channel monitoring multiplexer
GPIO function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI-compatible serial interface
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards
FUNCTIONAL BLOCK DIAGRAM
DVCC
TEMP_OUT
PEC
TEMP
SENSOR
CONTROL
REGISTER
VDD
MON_IN1
8
GPIO
REGISTER
2
n
n
SYNC
SCLK
n
SERIAL
INTERFACE
X1 REGISTER
M REGISTER
C REGISTER
n
X1 REGISTER
M REGISTER
C REGISTER
TO
MUX 2s
n
A/B
MUX
n
n
·
·
·
BIN/2SCOMP
SDI
14
n
n
MON_OUT
LDAC
A/B SELECT 8
REGISTER
n
MUX
GPIO
AGND DGND
n = 16 FOR AD5362
n = 14 FOR AD5363
8
VOUT0 TO
VOUT7
6
MON_IN0
VSS
·
·
·
·
·
·
·
·
·
n
n
A/B
MUX
n
X2B REGISTER
MUX
2
n
n
STATE
MACHINE
n
X2A REGISTER
X2B REGISTER
MUX
2
n
C REGISTER
n
n
n
X1 REGISTER
M REGISTER
C REGISTER
·
·
·
·
·
·
n
DAC 3
REGISTER
OUTPUT BUFFER
AND POWERDOWN CONTROL
DAC 3
TO
MUX 2s
n
A/B
MUX
n
n
·
·
·
n
n
VOUT0
VOUT1
VOUT2
VOUT3
SIGGND0
VREF1
n
·
·
·
n
AD5362/
AD5363
M REGISTER
DAC 0
n
A/B SELECT 8
REGISTER
X1 REGISTER
VREF0
·
·
·
·
·
·
n
A/B
MUX
OFS1
REGISTER
n
BUFFER
OFFSET
DAC 1
GROUP 1
BUFFER
X2A REGISTER
X2B REGISTER
MUX
2
n
n
DAC 4
REGISTER
·
·
·
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX
2
n
n
·
DAC 7
REGISTER
OUTPUT BUFFER
AND POWERDOWN CONTROL
DAC 4
n
DAC 7
·
·
·
OUTPUT BUFFER
AND POWERDOWN CONTROL
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND1
05762-001
n
GROUP 0
OUTPUT BUFFER
AND POWERDOWN CONTROL
n
·
·
·
BUSY
CLR
DAC 0
REGISTER
·
·
·
14
8
BUFFER
OFFSET
DAC 0
BUFFER
X2A REGISTER
SDO
RESET
OFS0
REGISTER
14
Figure 1.
Rev. A
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