All-surface Inspection for 3D-interconnects and TSV Manufacturing0 pages

INSPECTION

ANALYSIS

METROLOGY

APPLICATION NOTE

All-surface Inspection for 3D-interconnects and TSV Manufacturing
Rolf Shervey (presented at iwlpc 2009)
ABSTRACT

The need to inspect the topside, edge/bevel and backside of wafers at various stages of the semiconductor manufacturing process
has been driven by device manufacturers continuing the push to 100% wafer-surface utilization for active die. As a result, the
wafer-edge exclusion is becoming a thing of the past. With requirements for improving yield, thereby reducing costs, coming
to the forefront, processing challenges are simultaneously increasing. The effect of adding knowledge about topside, bevel and
backside-specific process phenomenon can be utilized not only in killer defect detection, but also in process improvement that
ultimately drives yield improvement.
Once-new processes such as immersion lithography and deposition of high-k dielectric films have driven the development of
wafer edge inspection technologies. As these processes become mainstream to semiconductor manufacturing, the next big
drivers for continuous improvement inspection and metrology equipment (and the application of that equipment) will include
the 3D-interconnects (3DIC) initiatives. Interconnects are one of the industry’s most difficult challenges: they involve depositing
metal into deep and narrow microscopic holes etched into a chip. 3DIC has specific needs for yield-enhancing information and
analysis which can be addressed by the next generation of all-surface inspection equipment.
Wafer-Level and Chip-Scale Packaging brought the concept of re-introducing a “back-end wafer” back into the front-end
process for RDL deposition and subsequent steps, and this is being seen again in the 3DIC/TSV development path. There is
much key learning in inspection and metrology that can be applied to these parallels, which if shared and applied correctly will
result in a shorter learning curve as 3DIC/TSV processes become standardized.

INTRODUCTION

3D interconnects are important because of the push towards
faster, more functional devices that are simultaneously
smaller, and more power efficient. Connecting chips with
discrete functions in a highly parallel way, and using the same
PCB real-estate is the end goal. For example, by integrating
memory above a processor die with a 1,000 “pins” (or TSVs)
parallel connection can reduce power consumption in the
interconnect to less than 1/10th that of a conventional
interconnect.1
TSVs may be the vehicle the industry uses to extend
Moore’s law by allowing us to sidestep the issue of shrinking
the transistor pitch altogether. TSVs promise the best
advantages of System-on-Chip (SoC) and System-in-Package
(SiP) together while achieving the optimum balance of
functionality, low cost, and the shortest time to market among
all serious alternatives.

Through-Silicon Vias
(TSVs) will be the 3D
interconnects’ method of
choice for future generations
of devices because of the
many advantages offered,
chief among them being
the higher densities of
Figure 1 - TSV cross-section (SEM
interconnects possible. This
image)
results in faster devices
with lower power consumption. There is also the ability to
manufacture the interconnects in-situ or along with die level
packaging processes, instead of requiring separate device-level
integration at wire bonding.
This paper discusses the applications for inspecting all surfaces
of semiconductor wafers during various steps in the 3D
interconnects and TSV manufacturing cycle. Inspections were
performed on a Rudolph Technologies AXi™-935 E30/B30
Advanced Macro-Defect Inspection system at SEMATECH’s

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