Xtensa LX4 Product Brief0 pages

PRODUCT BRIEF

Xtensa LX4 Customizable DPU

High Performance with Flexible I/Os and Wide Data Fetches
FEATURES

BENEFITS

Highly efficient, small, low-power 32-bit base architecture

Configurable over a wide range of pre-verified options
including 10 different DSP options

Extend with designer-defined application-specific instructions, execution units and register files

Virtually unlimited I/O bandwidth with designerdefined FIFO, GPIO and Lookup interfaces

Selectable 5– or 7-stage pipeline depth

Local memories configurable up to 8MB with option for
parity or ECC
Up to 128b wide instructions and up to two 512b wide
load/stores and Hardware Prefetch Unit

Complete matching development tool chain automatically generated for each core

Implement hardware for complex dataplane processing
dramatically faster than with pure RTL methods
High bandwidth data flow through processor with flexible I/O interfaces that bypass the system bus
Quickly and easily scale hardware architecture with
task-customized processors
Lower verification effort with pre-verified correct-byconstruction RTL generation
Post-silicon programmability
Accurate high-speed processor and system simulation
models automatically created for software development
Higher code density from efficient 16/24-bit ISA leads
to memory savings
Mature, highly-optimizing C/C++ compiler means you
can work at the ‘C’ level for most applications

Processors for the Challenges of the SOC Dataplane
In today’s complex SOC designs, processors can be found in
many places throughout the chip to add programmability for
added flexibility. While most processors do a good job with
control functions, they often fail at the complex dataplane processing tasks. That’s why designers often turn to RTL blocks
for the complex “heavy lifting” SOC tasks. The problem with
those RTL blocks is that they take too long to design, take
even longer to verify, and are not programmable.

What’s needed are processors that can be customized for
the task at hand with just the functions, registers and
datapath required. In order to provide enough data bandwidth to and from other system blocks, the processor
must provide direct connectivity with arbitrary widths and
predictable latency without using the system bus.
Tensilica’s Xtensa LX4 DPU (dataplane processing unit)
was designed from the start to be a basic building block in
SOC designs. It is ideal for handling complex computeintensive DSP applications where an RTL implementation
may be the only other option. Xtensa LX4 DPUs are configurable and extensible to meet application requirements
exactly.
Configurable: You are offered a menu of pre-verified
checkbox and drop-down options ranging from memory
size and width to complex DSP functions.

Xtensa LX4: Flexible direct connections allow RTL-like
throughput

Extensible: You can use our TIE (Tensilica Instruction
Extension) methodology, based on the Verilog language,
to implement the datapath elements in the processor pipeline. The control FSM (finite state machine) can be implemented as software running on the processor. Just specify
the functional behavior of the new datapath and the RTL is
automatically generated, along with the full matching software toolchain and models.